1. Field of the Invention
The present invention refers to a method for manufacturing field-effect metal oxide semiconductor transistors or, more briefly, MOS transistors.
2. Description of the Related Art
As is known, for the manufacture of MOS transistors the CMOS technology can conveniently be used making it possible to produce on the same chip, typically in silicon, both P-channel and N-channel MOS transistors. For example, manufacture of a MOS transistor envisages the provision of an insulated gate electrode on a chip, using photolithographic techniques, including a conductive layer (typically doped polysilicon) deposited on a layer of insulating material (for example, silicon dioxide) and the formation, by means of ionic implantation, of a drain active region and a source active region.
Conventional CMOS technology has the advantage of high integrability and permits fabrication of high speed devices. It should be noted that the use of MOS transistors for high frequency applications is favored by their reduced dimensions, obtained thanks to present-day integration technologies, which make it possible to reduce the internal capacity of said devices (in particular, gate capacity) and, therefore, to raise the cut-off frequencies of said transistors.
Furthermore, conventional MOS transistors may possess high trans-conductance due to reduced thickness of the gate oxide and silicidation of the source and drain active regions and gate polysilicon.
Concerning this, U.S. Pat. No. 6,492,234, which is incorporated by reference herein in its entirety, describes a method of selective silicidation of MOS active regions. The silicidation of a portion of the active region makes it possible to reduce its resistivity.
However, conventional MOS transistors do not provide adequate performance for radio frequency power applications but are suitable only for low power uses. It should be noted that, as a result of this, the power amplifiers used for cellular phone systems are manufactured using other technologies. For example, cell phones which operate in the GSM standard systems (Global System for Mobile Communications) or with the WCDMA (Wideband Division Code Multiple Access) standard, typically use gallium arsenide power amplifiers (GaAsFET).
The use of MOS transistors, such as those that can be obtained by CMOS technology, as power amplifiers is mainly hindered by three disadvantages.
The first disadvantage is represented by the low breakdown voltage between source and drain, BV, of the known MOS transistors which cannot withstand the working voltages typical of power applications.
Furthermore, said MOS transistors are not sufficiently reliable in the face of the phenomenon of injection of hot carriers into the gate oxide.
With reference to the known LDMOS transistors for power applications (Lateral Double diffused MOS), it should be noted that these have the disadvantage of difficult compatibility with the CMOS technology. This type of compatibility is practically an obligatory requirement since it would permit integration on a single chip of transistors used for power amplification and either P or N channel transistors performing logic functions.